4 chen y y , upadhyaya s j , cheng c h . a comprehensive reconfiguration scheme for fault - tolerant vlsi wsi array processors 為了應(yīng)對這一問題,容錯技術(shù)不得不被引入,以提高系統(tǒng)的可靠性。
This design can provide a high - speed path to a set of sharc parallel array processor . between this parallel processor and an analog signal acquisition module , the designed system can realize real time transmission 本設(shè)計的目的在于為一套sharc并行處理陣列機(jī)提供高速的數(shù)據(jù)通道,使其能與模擬信號采集模塊進(jìn)行實時的數(shù)據(jù)傳輸。